Growing research and development efforts are being made for faster semiconductor device with an emphasis put on MES (metal-semiconductor) field-effect transistors and heterojunction field-effect transistor using two-dimensional electron gas.
In general, a MES field-effect transistor using a gallium arsenide (GaAs) layer has a channel region doped to an impurity atom concentration of about 2.times.10.sup.17 cm.sup.-3, so that a shift in the threshold voltage tends to take place when shortening the gate length thereof so as to achieve a faster operation. The shift in the threshold voltage gives rise to deteriorate the reliability of the transistor. Moreover, the MES field-effect transistor suffers a small transconductance because of the low carrier density of the channel.
For a solution of these problems inherent in the MES field-effect transistor, a MES field-effect transistor is disclosed in IEEE Transaction on Electron Devices vol. 31, No. 8 1984, page 1032. The MES field-effect transistor disclosed in the above mentioned paper has a channel region doped to an impurity atom concentration of about 5.times.10.sup.18 cm.sup.-3 in order to prevent the field effect transistor from the shift in the threshold voltage and enhance the transconductance thereof, however problems are encountered in low breakdown voltages at the gate and the junction between the drain and the channel region due to heavily doped impurity atoms below the gate electrode. Moreover, it is impossible to produce a channel with a carrier density higher than the impurity atom concentration of about 5.times.10.sup.18 cm.sup.-3, so that the MES field-effect transistor has another problem in small current driving capability. Another prior-art MES field-effect transistor is disclosed by H. Dambkes et al in "GaAs-MESFETs WITH HIGHLY DOPED (10.sup.18 cm.sup.-3) CHANNELS-AN EXPERIMENTAL AND NUMERICAL INVESTIGATION", IEDM Technical Digest, 1983, pages 621 to 624, in which Dambkes et al propose the MES field-effect transistor with heavily doped channel region of about 1.5.times.10.sup.18 cm.sup.-3 which is free from the disadvantages due to the short-channel effects, but the proposed MES field-effect transistor also suffers a small amount of output current. Further, the heavily doped channel region leads to a problem in low controllability over the threshold voltage during fabrication process.
On the other hand, a heterojunction field-effect transistor having AlGaAs/GaAs structures generally has a large transconductance but suffers a small current driving capability due to the carrier density lower than about 1.times.10.sup.12 cm.sup.-3 as stated in IEEE Transaction on Electron Devices vol. 31, No.1 1984, page 29. A typical heterojunction field-effect transistor is described in Japanese Publication of Examined Application No. 53714/1984 and comprises a semi-insulating substrate, a multi-layer structure consisting of a doped barrier layer of aluminum gallium arsenide and a channel layer of gallium arsenide for providing a heterojunction therebetween, and gate, source and drain electrodes formed on the multi-layer structure. The heterojunction field-effect transistor described in the Japanese Publication of Examined Application uses the aforesaid multi-layer structure to produced a two-dimensional electron gas along the heterojunction between the doped barrier layer and the channel layer for a faster operation, but the doped barrier layer leads to problems in low controllability over the threshold voltage during fabrication process and in low breakdown voltage. Another heterojunction field-effect transistor is disclosed by P. M. Solomon et al in "A GaAs Gate Heterojunction FET", IEEE Electron Device Letters, vol. EDL-5, No.9, September 1984, pages 379 to 381. The heterojunction field-effect transistor proposed by P. M. Solomon et al comprises a semi-insulating substrate, a 1-micron undoped gallium arsenide buffer layer grown on the substrate, a 60-nm layer of undoped aluminum gallium arsenide (A.sub.0.4 Ga.sub.0.6 As) grown on the buffer layer, a 0.4 micron gate layer of n.sup.+ gallium arsenide doped with silicon atoms and a gate electrode of molybdenum, and operates at an improved speed. However, the field-effect transistor basically operates in normally-off mode only, so that the structure is not applicable to some integrated circuits. Another heterojunction field-effect transistor is disclosed by N. C. Cirillo, Jr. et al in "Realization of n-Channel and p-Channel High-Mobility (Al,Ga)As/GaAs Heterostructure Insulating Gate FET's on a Planar Wafer Surface", IEEE ELECTRON DEVICE LETTERS, Vol. EDL-6, No. 12, December 1985, pages 645 to 647. The field-effect transistor proposed by N. C. Cirillo, Jr. comprises a semi-insulating gallium arsenide substrate, a 500-nm thick p.sup.- -type gallium arsenide buffer grown on the semi-insulating substrate, a 45-nm thick undoped p.sup.- Al.sub.0.3 Ga.sub.0.7 As gate insulator layer grown on the buffer, source and drain region formed in the gate insulator layer by selective ion implantation and a WSi gate formed on the gate insulator layer. However, this heterojunction field-effect transistor also operates in normally-off mode only, so that this structure merely has a limited application similar to that proposed by P. M. Solomon. Still another structure of a field-effect transistor is disclosed in Japanese Publication of Unexamined Application No. 61265/1976. This field-effect transistor comprises a substrate formed of an n-type gallium arsenide, a surface inactivation film of gallium nitride formed on the substrate and having a wider band gap than that of the substrate. The surface inactivation film is grown by vapor phase epitaxy and the resultant structure aims at improvement in interface condition between the substrate and the surface inactivation film.
The closest structure may be disclosed by the Applicant in the specification of the U.S. patent application Ser. No. 024,213 filed on Mar. 10, 1987. The heterojunction field-effect transistor described in the specification is fabricated on a semi-insulating substrate of gallium arsenide and comprises a buffer layer of gallium arsenide formed on the semi-insulating substrate, an n-type gallium arsenide layer formed on the buffer layer and having a high impurity atom concentration, a high-purity aluminum gallium arsenide layer formed on the n-type gallium arsenide layer and a gate electrode formed on the high-purity aluminum gallium arsenide layer. In the heterojunction field-effect transistor, a large amount of electrons takes place at the interface between the high-purity aluminum gallium arsenide layer and the n-type gallium arsenide layer under a sufficiently high gate voltage, and the field-effect transistor can operate at an improved speed with a high withstand voltage. However, the heterojunction field-effect transistor described in the specification has a room for improvement in speed and transconductance.